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공공누리This item is licensed Korea Open Government License

Atomistic modeling of metallic nanowires in silicon
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Scanning tunneling microscope (STM) lithography has recently demonstrated the ultimate in device scaling with buried, conducting nanowires just a few atoms wide and the realization of single atom transistors, where a single P atom has been placed inside a transistor architecture with atomic precision accuracy. Despite the dimensions of the critical parts of these devices being defined by a small number of P atoms, the device electronic properties are influenced by the surrounding 104 to 106 Si atoms. Such effects are hard to capture with most modeling approaches, and prior to this work no theory existed that could explore the realistic size of the complete device in which both dopant disorder and placement are important. This work presents a comprehensive study of the electronic and transport properties of ultra-thin (sub-10 nm wide) monolayer highly P delta-doped Si (Si:P) nanowires in a fully atomistic self-consistent tight-binding approach. This atomistic approach covering large device volumes allows for a systematic study of disorder on the physical properties of the nanowires. Excellent quantitative agreement is observed with recent resistance measurements of STM-patterned nanowires [Weber et al., Science, 2012, 335, 64], confirming the presence of metallic behavior at the scaling limit. At high doping densities the channel resistance is shown to be insensitive to the exact channel dopant placement highlighting their future use as metallic interconnects. This work presents the first theoretical study of Si:P nanowires that are realistically extended and disordered, providing a strong theoretical foundation for the design and understanding of atomic-scale electronics.
Nano electronics; Si:Psystems; Metallic nanowires; Tight-binding approach
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7. KISTI 연구성과 > 학술지 발표논문
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